1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Description of Related Art
Typically, a semiconductor device includes a semiconductor substrate, and an electronic element and a wiring that are formed over the main surface of the semiconductor substrate. The semiconductor device may include an interlayer dielectric film. A silicon oxide film is widely used as the interlayer dielectric film. A variety of methods are available for forming a silicon oxide film. For example, a silicon oxide film may be formed by reacting a silicon compound such as silane or the like with hydrogen peroxide by a CVD method (hereinafter referred to as xe2x80x9cplanarizing silicon oxide filmxe2x80x9d). For example, this method is described in Japanese Laid-open Patent Application HEI 9-102492. The planarizing silicon oxide film has an excellent planarization characteristic.
An interlayer dielectric film that includes a planarizing silicon oxide film may have variations in film thickness depending on locations on the main surface of the semiconductor substrate. For example, the variations occur due to the following reasons.
First, the main surface of the semiconductor substrate includes a region where wirings are formed with a high wiring density and a region wherein wirings are formed with a low wiring density. The thickness of the planarizing silicon oxide film formed over the high wiring density region is generally greater than the thickness of the planarizing silicon oxide film formed over the low wiring density region, due to a high level of flowability of the planarizing silicon oxide film.
Secondly, as the number of wiring layers increases, the number of interlayer dielectric films typically increases. Each interlayer dielectric film has variations in thickness. Such thickness variations in a plurality of the interlayer dielectric films may add up where the interlayer dielectric films overlap one another. As a result, the added thickness variation becomes greater at an upper level than at a lower level of the interlayer dielectric films. As the thickness variation becomes greater, a step difference in an interlayer dielectric film becomes larger.
When a through hole is formed in an interlayer dielectric film, a resist is used. A focus margin in exposure with respect to the resist becomes smaller when the step difference in the interlayer dielectric film becomes larger. As a result, the resolution at the resist lowers. As a consequence, a designed shape of a through hole may not be formed, or in the worst case, a through hole may not be formed at all.
It is an object of the present invention to provide a semiconductor device and a method for manufacturing a semiconductor device having a structure in which a focus margin does not become smaller.
A semiconductor device in accordance with one embodiment of the present invention has a semiconductor substrate having a main surface including a first region and a second region, and an interlayer dielectric film formed over the first region and the second region. In accordance with one embodiment of the present invention, for example, at least a bonding pad, a power source line, a test pattern or the like is formed in the first region. Also, in accordance with one embodiment of the present invention, at least a logic circuit, an analog circuit, a memory circuit or the like is formed in the second region.
The interlayer dielectric film defines a first through hole over the first region and a second through hole over the second region. In a preferred embodiment, the interlayer dielectric film has a maximum thickness over the first region. The interlayer dielectric film over the second region has a thickness that is about 90-50% of the maximum thickness. More preferably, the interlayer dielectric film over the second region has a thickness that is about 80-50% of the maximum thickness. In a preferred embodiment, an aperture area of the first through hole is greater than that of the second through hole.
It is noted that the problem of reduced focus margin is substantially eliminated when he film thickness over the second region is greater than about 90% of a maximum film thickness over the first region. When the film thickness over the second region is smaller than about 50%, the capacitance between metal wirings (such as for example, aluminum wirings) becomes large. As a result, the electrical characteristics of the semiconductor device deteriorate. Also, when a difference in the film thickness of the interlayer dielectric film becomes larger, an etching operation to form through holes becomes more difficult.
In a semiconductor device in accordance with one embodiment of the present invention, an aperture area of the first through hole is greater than an aperture area of the second through hole. As a result, a resist can be exposed with a focus margin for forming the second through hole. Thus, the focus margin does not become too small. The details will be described below with reference to preferred embodiments of the present invention.
In a semiconductor device in accordance with the present invention, a member that reduces the volume of the first through hole may preferably be formed in the first through hole due at least in part to the following reasons. An aperture area of the first through hole is greater than an aperture area of the second through hole. Accordingly, the first through hole has a greater volume than that of the second through hole. When conductive films are formed in the first and second through holes, the amount of the conductive film may not be sufficient to fill the first through hole, and there is a likelihood that the conductive film formed in the first through hole may have a recess. The recess results in a step difference in the interlayer dielectric film. The member formed in the first through hole can solve such problems as described above.
In one embodiment, the member may be formed as follows. The first through hole is formed by etching the interlayer dielectric film in a manner that the interlayer dielectric film in a column form remains at a center of the first through hole. The remaining column-like interlayer dielectric film occupies the internal space of the first through hole to serve as a member,
In accordance with one embodiment of the present invention, a semiconductor device may be manufactured by the following method. A semiconductor device formed by a manufacturing method in accordance with the embodiment of the present invention has a semiconductor substrate having a main surface including a first region and a second region, and an interlayer dielectric film formed over the first region and the second region. The interlayer dielectric film defines a first through hole over the first region and a second through hole over the second region. The manufacturing method includes the following steps:
(a) The interlayer dielectric film is formed over the first region and the second region, wherein the interlayer dielectric film has a maximum thickness over the first region, and the interlayer dielectric film has a thickness that is 90-50% of the maximum thickness over the second region;
(b) A resist is formed over the interlayer dielectric film;
(c) The resist is exposed to light to form a pattern in the resist, wherein the resist pattern has an aperture for the first through hole and an aperture for the second through hole, wherein an area of the aperture for the first through hole is greater than an area of the aperture for the second through hole; and
(d) The first through hole and the second through hole are formed by selectively etching the interlayer dielectric film using the resist as a mask.
The exposure in step (c) is conducted by, for example, one of a reduction projection exposure, an equal magnification (1:1) projection exposure and a scanning-type reduction projection exposure.
In a semiconductor device in accordance with one embodiment of the present invention, the interlayer dielectric film may preferably include a first silicon oxide film that is formed by a polycondensation reaction between a silicon compound and hydrogen peroxide.
In accordance with one embodiment of the present invention, step (a) may include step (e) in which the first silicon oxide film is formed by the reaction of a silicon compound with hydrogen peroxide using a CVD method. As a result, the formed interlayer dielectric film has an excellent planarization characteristic. It has been confirmed that the first silicon oxide film formed by this manufacturing method has a high flowability and a high self-planarization characteristic. This phenomenon is believed to take place due to the following mechanism. When a silicon compound and hydrogen peroxide are reacted by the CVD method, silanol is formed in a vapor phase, and the silanol deposits on the surface of the wafer to provide a film having a high flowability.
For example, when monosilane is used as a silicon compound, silanol is formed by reactions defined by formulas (1) and (1)xe2x80x2 as follows:
SiH4+2H2O2xe2x86x92Si(OH)4+2H2xe2x80x83xe2x80x83Formula (1)
SiH4+3H2O2xe2x86x92Si(OH)4+2H2O+H2xe2x80x83xe2x80x83Formula (1)xe2x80x2
Silanol formed by the reactions defined by Formulas (1) and (1)xe2x80x2 becomes silicon oxide as a result of disconnection of water by a polycondensation reaction defined by Formula (2) as follows:
Si(OH)4xe2x86x92SiO2+2H2Oxe2x80x83xe2x80x83Formula (2)
The silicon compounds include, for example, inorganic silane compounds, such as, monosilane, disilane, SiH2Cl2, SiF4 and the like, and organo silane compounds, such as, CH3SiH3, tripropyle-silane, tetraethylorthosilicate and the like.
Step (e) described above may preferably be conducted by a reduced pressure CVD method at temperatures of about 0-20xc2x0 C. when the silicon compound is an inorganic silicon compound, and at temperatures of about 0-150xc2x0 C. when the silicon compound is an organic silicon compound. If the temperature during the film-forming step is higher than the upper limit of the above-described temperature ranges, the polycondensation reaction defined by Formula (2) progresses excessively. As a result, the flowability of the first silicon oxide film lowers, and therefore it is difficult to obtain good planarization. On the other hand, if the temperature is lower than the lower limit of the above-described temperature ranges, the control of a film-forming apparatus becomes difficult. For example, water formed from the reaction adsorbs on surfaces within the chamber, and dew condensation occurs outside the chamber.
The first silicon oxide film may preferably be formed with a thickness that sufficiently covers step differences of the underlying layer. The minimum thickness of the first silicon oxide film depends on the height of protrusions and recesses of the underlying layer, and is preferably between about 300 and 1500 nm. If the film thickness of the first silicon oxide film exceeds over the above-described upper limit, cracks may occur due to stresses of the film itself.
The interlayer dielectric film may include any one of films other than the first silicon oxide film described above. Such films include, for example, SOG films (organic or inorganic) and silicon oxide films that are formed by reacting an organic silane, such as for example, TEOS with ozone or water.
In a semiconductor device in accordance with one embodiment of the present invention, the interlayer dielectric film may preferably include a second silicon oxide film that is located over the first silicon oxide film and serves as a cap layer.
In accordance with one embodiment of the present invention, step (a) may include step (f) in which a second porous silicon oxide film that serves as a cap layer is formed over the first silicon oxide film by reacting a silicon compound with at least one of oxygen and a compound including oxygen using a CVD method.
An impurity, such as, phosphorous, boron or the like, may preferably be added to the second porous silicon oxide film. More preferably, boron is added to the second porous silicon oxide film. As a result, the film can relieve stresses by weakening the molecular bonding force between Si and O molecules of the silicon oxide that forms the film. In other words, the layer becomes moderately soft but hard enough to resist to cracks. One important role of the second silicon oxide film is a function in which the impurity such as phosphorous contained in the silicon oxide film functions as a getter of mobile ions, such as alkali-ions which have a deteriorating effect on the element device-reliability characteristics. The impurity concentration of the impurity contained in the second silicon oxide film may preferably be about 1-6 weight %, in consideration of the gettering function and the stress relieving function of the film.
Also, the second silicon oxide film has a compression stress of about 100-600 MPa, and therefore has a function in preventing the generation of cracks due to an increased tensile stress that is caused in the first silicon oxide film when it undergoes polycondensation. Further, the second silicon oxide film has a function in preventing the first silicon oxide film from absorbing moisture.
The second silicon oxide film may preferably be formed by a plasma CVD method with a high frequency at temperatures of about 300-450xc2x0 C. This process is effective in disconnecting water content from the first silicon oxide film.
The compound including oxygen that is used for forming the second silicon oxide film may be oxygen (O2), and more preferably nitrogen monoxide (N2O). By the use of nitrogen monoxide as a reactant gas, the nitrogen monoxide in the form of a plasma likely reacts with hydrogen bonds (xe2x80x94H) of the silicon compound that forms the first silicon oxide film. As a result, disconnection of gasification components (hydrogen, water) from the first silicon oxide film is promoted even while the second silicon oxide film is being formed.
Alternatively, the second silicon oxide film may be formed by a normal pressure CVD method at temperatures of about 300-550xc2x0 C., instead of the plasma CVD method. In this case, ozone may preferably be used as a compound including oxygen that is utilized for forming the second silicon oxide film.
Also, before the second silicon oxide film is formed, the first silicon oxide film may preferably be exposed to an ozone atmosphere. Since ozone likely reacts with hydrogen bonds (xe2x80x94H) and hydroxyls (xe2x80x94OH) of the silicon compound that forms the first silicon oxide film, disconnection of hydrogen and water from the first silicon oxide film is promoted.
The thickness of the second silicon oxide film is preferably about 100 nm or greater in consideration of the planarization, prevention of cracks and the thickness of the interlayer dielectric film.
In one embodiment, a tapered through hole is formed in the interlayer dielectric film including the first silicon oxide film and the second silicon oxide film that is obtained in step (f). The tapered through hole has aperture diameters that gradually reduce from a mouth section to a bottom of the through hole. In the present embodiment, the etching speed for the first silicon oxide film is slightly slower than the etching speed for the second silicon oxide film, and the first silicon oxide film, and the second silicon oxide film are bonded well to each other at their boundaries. As a result, the through hole has a generally linear taper wall without step differences in the wall. An aluminum film or an aluminum alloy film can be filled in such a tapered through hole, for example, by sputtering, and thus a contact structure with an excellent conductivity is formed.
The through hole described above may be formed by an anisotropic dry etching. Also, a tapered through hole with a curved surface in an upper end section of the through hole may be formed by a combination of an isotropic wet etching and an anisotropic dry etching.
In a semiconductor device in accordance with one embodiment of the present invention, the interlayer dielectric film may preferably include a third silicon oxide film that serves as a base layer that is located under the first silicon oxide film.
The base layer has a passivation function that prevents migration of water and excess impurities from the first silicon oxide film to an underlying layer below the base layer (a main surface of a semiconductor substrate when there is no underlying layer). Also, the base layer has a function in increasing the cohesiveness between the first silicon oxide film and an underlying layer below the base layer (a main surface of a semiconductor substrate when there is no underlying layer).
When a gettering effect is required to get alkali-ions, an impurity, such as, phosphorous in the amount of about 1-6 weight % may be added to the third silicon oxide film that forms the base layer. Alternatively, for example, a PSG film containing phosphorous in the amount of about 1-6 weight % may be formed between the third silicon oxide film and the first silicon oxide film.
In accordance with one embodiment of the present invention, step (a) may include step (g) in which the third silicon oxide film that serves as a base layer is formed under the first silicon oxide film by reacting a silicon compound with at least one of oxygen and a compound including oxygen using a CVD method.
A tapered through hole may be formed in the interlayer dielectric film including the first silicon oxide film and the third silicon oxide film that is obtained in the step (g). The tapered through hole has aperture diameters that gradually reduce from a mouth section to a bottom of the through hole. The etching speed for the first silicon oxide film is slightly faster than the etching speed for the third silicon oxide film that forms the base layer. As a result, the through hole has an appropriate linear taper. An aluminum film or an aluminum alloy film can be filled in such a tapered through hole by sputtering, and thus a contact structure with an excellent conductivity is formed.
The through hole described above may be formed by an anisotropic dry etching. Also, a tapered through hole with a curved surface in an upper end section of the through hole may be formed by a combination of an isotropic wet etching and an anisotropic dry etching.
A semiconductor device in accordance with one embodiment of the present invention may preferably include a wiring formed on the interlayer dielectric film. In a preferred embodiment, the wiring may include a barrier layer formed on surfaces of the first through hole, the second through hole and the interlayer dielectric film, and a conductive film formed on a surface of the barrier layer.
The method for forming a semiconductor device in accordance with one embodiment of the present invention includes, after step (d), the steps of forming a barrier layer serving as a part of the wiring on surfaces of the first through hole, the second through hole and the interlayer dielectric film, and a conductive film on a surface of the barrier layer that forms a part of the wiring.
The conductive film may preferably be formed from aluminum or an alloy containing aluminum as a main component.
A semiconductor device that includes the wiring in accordance with the present invention may be formed by the following steps. A first aluminum film composed of aluminum or an alloy containing aluminum as a main component is formed in the first and second through holes at temperatures of about 200xc2x0 C. or lower. Then, a second aluminum film composed of aluminum or an alloy containing aluminum as a main component is formed at temperatures of about 300xc2x0 C. or higher.
The alloy containing aluminum as a main component may be a two-component or a three-component alloy containing at least one of copper, silicon, germanium, magnesium, cobalt and beryllium.